Self-enclosed asymmetric interconnect structures

ABSTRACT

Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. The techniques provided are particularly useful, for instance, when lithography registration errors cause neighboring conductive features to be physically closer than expected, but can also be used when such proximity is intentional. In some embodiments, the techniques can be implemented using a layer of electromigration management material (EMM) and one or more insulator layers, wherein the various layers are provisioned to enable a differential etch rate. In particular, the overall etch rate of materials above the target landing pad is faster than the overall etch rate of materials above the off-target landing pad, which results in a self-enclosed conductive interconnect feature having an asymmetric taper or profile. The differential etch rate may result, for example, from configuration of the EMM layer, or from accompanying insulator layers having different etch rates.

RELATED APPLICATIONS

This patent application is a continuation of U.S. application Ser. No.13/976,456 filed Oct. 2, 2013, now U.S. Pat. No. 9,960,110, which is aU.S. National Stage Application of PCT/US2011/068159 filed Dec. 30,2011, each of which is incorporated by reference herein in its entirety.

BACKGROUND

In the manufacture of integrated circuits, interconnects are generallyformed on a semiconductor substrate using a copper damascene process.Such a process typically begins with a trench and/or via being etchedinto an insulator layer and then filled with copper metal to form theinterconnect. It is often desirable to stack multiple layers to form anintegrated circuit, by adding additional layers of insulator andmetal-filled features. In such cases, various interconnect features canbe used to electrically connect one layer to another, as desired for agiven integrated circuit design. However, as device dimensions continueto scale down, the features become narrower and closer together givingrise to a number of non-trivial problems.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example stacked conductive interconnect featureshowing an unlanded via caused by lithography registration error.

FIGS. 2A-I illustrate cross-section side views of a series of integratedcircuit structures showing formation of a self-enclosed interconnectfeature in accordance with an embodiment of the present invention.

FIGS. 3A-G illustrate cross-section side views of a series of integratedcircuit structures showing formation of a self-enclosed interconnectfeature in accordance with another embodiment of the present invention.

FIGS. 4A-G illustrate cross-section side views of a series of integratedcircuit structures showing formation of a self-enclosed interconnectfeature in accordance with another embodiment of the present invention.

FIG. 4G′ illustrates a cross-section side view of an integrated circuitstructure having a self-enclosed interconnect feature in accordance withanother embodiment of the present invention.

FIG. 5A shows a specific example embodiment where the underlying metallanding pad is a metal line of a lower layer in a dynamic random accessmemory (DRAM) integrated circuit structure.

FIGS. 5B and 5C each illustrates an expanded view of the unlanded viashown in FIG. 5A, and configured in accordance with one embodiment ofthe present invention.

FIGS. 6A-B each illustrates electrical properties of various insulatormaterials that may be used in accordance with some embodiments of thepresent invention.

FIG. 7A illustrates a simulation comparing electrical field strengthsand locations in a conventional stacked conductive interconnectstructure and a stacked conductive interconnect structure configured inaccordance with an embodiment of the present invention.

FIG. 7B graphically illustrates a reduction in electrical field strengthfor stacked conductive interconnect structures configured in accordancewith an embodiment of the present invention, relative to conventionalstacked conductive interconnect structures.

FIG. 8 illustrates an example computing system having one or moredevices implemented with conductive structures formed in accordance withan embodiment of the present invention.

As will be appreciated, the figures are not necessarily drawn to scaleor intended to limit the claimed invention to the specificconfigurations shown. For instance, while some figures generallyindicate straight lines, right angles, and smooth surfaces, an actualimplementation of a structure may have less than perfect straight lines,right angles, and some features may have surface topology or otherwisebe non-smooth, given real world limitations of the processing equipmentand techniques used. In short, the figures are provided merely to showexample structures.

DETAILED DESCRIPTION

Techniques are disclosed that enable improved shorting margin betweenunlanded conductive interconnect features (e.g., vias) and neighboringconductive features of an integrated circuit. As will be appreciated inlight of this disclosure, an unlanded interconnect feature is one wherepart of the feature is on its target landing pad and part of the featureis not on the target landing pad. The area adjacent to the intendedtarget landing pad is generally referred to herein as the off-targetlanding pad. The techniques provided are particularly useful, forinstance, when lithography registration errors cause neighboringconductive features to be physically closer than expected, but can alsobe used when such proximity is intentional (such as in integratedcircuits where high packing density is desired). In some embodiments,the techniques can be implemented using a layer of electromigrationmanagement material (EMM) and one or more insulator layers, wherein thevarious layers are provisioned to enable a differential etch rate. Inparticular, the overall etch rate of materials above the target landingpad is faster than the overall etch rate of materials above theoff-target landing pad, which results in a self-enclosed conductiveinterconnect feature having an asymmetric taper or profile. Theresulting asymmetric taper effectively increases the shorting marginwith respect to that interconnect feature and a conductor neighboringthe landing pad of the interconnect feature. The differential nature ofthe etch rate may result, for example, from the specific configurationof the EMM layer itself, and/or from a combination of insulator layers(or other suitable material layers) having different etch rates.

General Overview

As previously explained, it is often desirable to stack multiple layersof an integrated circuit by adding additional layers of insulator andmetal-filled features, using standard deposition-lithography techniques.The scaling of such conventional processes to provide smaller featuresizes can be difficult because of, for example, increased significanceof lithography registration errors. For instance, FIG. 1 shows anexample interconnect structure illustrating the problematic shiftingassociated with lithography registration errors. As can be seen, the viaintended to connect the upper metal (e.g., M3) with the lower metal A(e.g., M2) is misaligned and therefore shifted closer to the neighboringlower metal B, thereby leaving a reduced distance D between theconductive features. This reduced spacing can lead to insufficientshorting margin and decreased time-dependent dielectric breakdown(TDDB), or even a complete short-circuit. Note that even when the viadoes not completely short to the neighboring conductor, the distance Dcan be decreased to a point where the thin insulator that separates themis not capable of withstanding the typical fields generated by, forinstance, a ˜1V power supply. The end result is yield fallout in thecase of shorting, or a reliability marginality when the space D isincapable of supporting the operating field. As will be appreciated,while specific example via and metal layers are used here forillustration purposes, this issue can exist at all lower metal layers(e.g., M1 through M9, etc) and in a more general sense, in anyintegrated circuit structure having multiple layers of conductivefeatures susceptible to insufficient shorting margin resulting fromlithography registration errors or high packing density.

Thus, and in accordance with one embodiment, techniques are provided forforming conductive interconnect features, such as through-vias anddamascene features (e.g., trench/via structures) for electricallyconnecting one layer of an integrated circuit to another layer of thatintegrated circuit. In some embodiments, the techniques are implementedin an integrated circuit structure that includes a layer ofelectromigration management material (EMM) or other suitable interveninglayer and one or more insulator layers, wherein the various layers areprovisioned to enable a differential etch rate. As will be apparent inlight of this disclosure, the differential nature of the etch rate mayresult from the specific configuration of the EMM layer itself, and/orfrom a combination of insulator layers having different etch rates. Aninsulator layer (e.g., continuous or multilayer) is deposited over theEMM layer, and an unlanded via or other conductive interconnect featurecan then be patterned and etched into that insulator layer. The etchrate is generally uniform until the EMM (or other suitable interveninglayer) is encountered. From that point on, the etch rate of the EMMand/or one or more of the provisioned insulator layers over theoff-target landing pad is slower than the etch rate of the EMM and/orinsulator material over the target landing pad, resulting in aself-enclosed via (SEV) or other interconnect feature having anasymmetric taper, thereby increasing the shorting margin with respect toits neighboring conductor.

In some such example cases, the EMM layer (or other suitable interveninglayer) is uniformly deposited over the underlying fill metal and abilayer insulator structure having base and cap insulator layers. Inthis example case, the EMM layer is provided uniformly over both thetarget and off-target landing pads, and therefore does not actuallycontribute to the differential etch rate. Rather, the differential etchrate results from the cap insulator layer having a slower etch rate thanthe base insulator layer, the cap insulator layer over the targetlanding pad having been removed during trench formation earlier in theprocess. Thus, the etch rate is generally uniform until the EMM isencountered. At that point, the overall etch rate of the EMM and capinsulator layer is slower than the overall etch rate of the baseinsulator layer and EMM layer, resulting in a self-enclosed interconnectfeature having an asymmetric taper, thereby increasing the shortingmargin with respect to its neighboring conductor. In some specific suchcases, for instance, the etch selectivity with respect to the base andcap layers is greater than 5:1, such that the cap insulator materialetches more than 5 times slower than the base insulator material for agiven base layer etch process. As will be appreciated, however, notethat etch selectivity will vary from one embodiment to the nextdepending on factors such as insulator materials chosen as well as layerthicknesses and etch chemistries and desired shorting margin, and theclaimed invention is not intended to be limited to any particular etchrate scheme. Rather, any etch rate scheme that enables an asymmetrictaper as described herein can be used (e.g., such as those where theetch selectivity with respect to the base and cap layers is greater than1:1, or greater than 2:1, etc). As will be further appreciated, theinsulator structure may have multiple layers (e.g., trilayer insulatorstructures having three types of insulator or other intervening materiallayers each associated with a desired etch rate), and one or more ofthose layers may impact the differential etch rate. Further note thatsome embodiments may be implemented without the EMM layer, and just havetwo or more different material layers (of insulator and/or othersuitable material layers) that provide the desired overall differentialetch rates to cause the asymmetric taper as described herein.

In other example embodiments, an EMM layer (or other suitableintervening layer) of variable thickness may be deposited over theinsulator structure and underlying fill metal, wherein the differentialetch rate effectively results from a thinner EMM layer at one or morepositions over the underlying fill metal (target landing pad) relativeto EMM layer thickness at positions over the insulator structure. In onespecific such embodiment, the EMM layer over the insulator material atone or more points is more than twice the thickness of the EMM layer atone or more points over the underlying fill metal. The etch rate isgenerally uniform until the EMM is encountered, with the variable EMMthickness resulting in a self-enclosed interconnect feature having anasymmetric taper, thereby increasing the shorting margin with respect toits neighboring conductor. In such cases, the insulator structure canhave any number of configurations, including those made from a singlecontinuous layer of insulator material, or those made with a bilayerconstruction having a base layer and a cap layer, or any other desiredmultilayer construction, so long as the ratio of overall etch rate ofmaterials over the target landing pad to overall etch rate of materialsover the off-target landing pad (for a given etch process) is greaterthan 1 (e.g., >2, or >3 . . . or >5, etc) and the desired asymmetrictaper is provided.

In other example cases, a uniform EMM layer (or other suitableintervening layer) is deposited over an insulator structure andpatterned during trench formation, prior to deposition of the lowermetal layer. The lower metal layer can then be deposited, and asubsequent insulator layer (e.g., continuous or multilayer) can then bedeposited over the patterned EMM layer and lower metal layer. Anunlanded via or other conductive interconnect feature can then bepatterned and etched into the insulator layer. As will be appreciated,the etch rate is generally uniform until the patterned EMM isencountered. However, the EMM (or other suitable intervening layer)etches more slowly than the insulator material or materials, resultingin a self-enclosed interconnect feature having an asymmetric taper,thereby increasing the shorting margin with respect to its neighboringconductor. To generate a self-enclosed interconnect structure inaccordance with some such embodiments, the ratio of overall etch rate ofmaterials over the target landing pad to overall etch rate of materialsover the off-target landing pad (for a given etch process) is greaterthan 1.

As will be appreciated, note that an electromigration barrier layer (EMMlayer) is not required in all embodiments. For instance, in some examplecases, a uniform cap or intervening layer of any desired material (e.g.,passivation material such as silicon nitride, diffusion barrier materialsuch as tantalum nitride, insulator material such as silicon dioxide ororganosilicate glass, or any other suitable material) is deposited overa base layer (e.g., continuous or multilayer) and patterned duringtrench formation, prior to deposition of the metal layer. The metallayer can then be deposited into the base layer, and a subsequent baselayer (e.g., continuous or multilayer) can then be deposited over thepatterned cap/intervening layer and metal. This subsequent base layermay also include a cap/intervening layer, if so desired. In any case, anunlanded via or other conductive interconnect feature can then bepatterned and etched into the subsequent base layer. As will beappreciated, the etch rate is generally uniform until the patternedcap/intervening layer is encountered. However, the cap/intervening layeretches more slowly than the base layer, resulting in a self-enclosedinterconnect feature having an asymmetric taper, thereby increasing theshorting margin with respect to its neighboring conductor. As will beappreciated in light of this disclosure, to generate a self-enclosedinterconnect structure in accordance with some such embodiments, theratio of overall etch rate of materials over the target landing pad tooverall etch rate of materials of the off-target landing pad (for agiven etch process) is greater than 1.

Thus, when subsequently provisioning an unlanded interconnect feature inaccordance with an embodiment of the present invention, the overall etchrate for materials at one or more points above the target landing pad isfaster than the overall etch rate for materials at one or more pointsabove the off-target landing pad, which results in a self-enclosedconductive interconnect feature having an asymmetric taper or profile.Numerous suitable EMM (sometimes referred to herein as electromigrationbarrier materials), insulator materials (sometimes referred to asdielectrics), metal/alloy materials (sometime referred to as fill metal,nucleation metal or seed metal), and/or any alternative interveningmaterial and, as well as numerous suitable fabrications processes (e.g.,wet/dry etching, lithography, chemical vapor deposition, atomic layerdeposition, spin-on deposition, or physical vapor deposition,electroplating, electroless deposition), can be used to implement anembodiment of the present invention.

Interconnect Structures with Bilayer Insulator

FIGS. 2A-I illustrate cross-section side views of a series of integratedcircuit structures showing formation of a self-enclosed interconnectfeature configured in accordance with an embodiment of the presentinvention.

As can be seen, FIG. 2A illustrates an interlayer dielectric (ILD) layerhaving a bilayer configuration that includes a base layer and a caplayer. As will be appreciated, the structure may be formed as part of,or otherwise on, a substrate and may be configured in a number of waysand using any number of materials, as will be appreciated in light ofthis disclosure. Each of the base and cap insulator layers can bedeposited using conventional processes, such as chemical vapordeposition (CVD), atomic layer deposition (ALD), spin-on deposition(SOD), physical vapor deposition (PVD), or other suitable depositionprocess, and then be planarized as commonly done (e.g., by way ofchemical mechanical planarization, or CMP). The base and cap insulatorlayer thicknesses can vary greatly, but in some example embodiments arein the range of 50 nm to 5000 nm for the base insulator layer and 2 nmto 200 nm for the cap insulator layer. Either or both of the base andcap insulator layers may comprise multiple sub-layers in some exampleembodiments (of the same or different materials), or may each be asingle layer. In still other embodiments, the base and cap layers areimplemented as a gradation of a single layer provided by a singledeposition method (e.g., the process conditions in a plasma chamber maybe altered to provide a density gradient such that there is no distinctinterface). Numerous insulator layer configurations can be used and theclaimed invention is not intended to be limited to any particular set ofmaterial systems or geometries.

Example insulator materials that can be used include, for instance,nitrides, oxides, oxynitrides, carbides, oxycarbides, polymers, silanes,siloxanes, or other suitable insulator materials. In some embodiments,the base insulator layer is implemented with ultra-low-k insulatormaterials and the cap insulator layer is implemented with low or high-kdielectric materials. Ultra-low dielectric materials may generally havegreater porosity and therefore a faster etch rate relative to densermaterials having higher dielectric constants. Example low-k dielectricmaterials includes silicon dioxide, carbon doped oxide (CDO), organicpolymers such as perfluorocyclobutane or polytetrafluoroethylene,fluorosilicate glass (FSG), and organosilicates such as silsesquioxane,siloxane, or organosilicate glass. Examples of ultra-low-k dielectricmaterials generally include any such low-k materials, but configuredwith pores or other voids to further reduce density and dielectricconstant. Examples of high-k dielectric materials include, for instance,hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanumaluminum oxide, zirconium oxide, zirconium silicon oxide, tantalumoxide, titanium oxide, barium strontium titanium oxide, barium titaniumoxide, strontium titanium oxide, yttrium oxide, aluminum oxide, leadscandium tantalum oxide, and lead zinc niobate.

In some specific example embodiments, the base insulator material canbe, for example, an ultra-low dielectric material such as a porous SiCOHhaving a dielectric constant k of less than 2.3 and porosity greaterthan 35 volume %. In such example cases, the cap insulator layer can be,for instance, a relatively denser SiCOH having a dielectric constant kin the range of about 2.8 to 3.0, and a porosity of less than 10 volume% or a plasma-enhanced CVD (PECVD) oxide (e.g., silicon dioxide) ornitride (e.g., silicon nitride). In a more general sense, the etch rateof the base insulator layer material is greater than the etch rate ofthe cap insulator layer material. Continuing with the specific exampleusing porous SiCOH for the base layer and denser SiCOH for the caplayer, an etch process with greater than 2:1 selectivity in the etch ofthe cap and base layers is achieved. As will be appreciated in light ofthis disclosure, use of bilayer structure having an ultra-low-k/porousbase layer provides a fast etch over the target landing pad, and arelatively higher-k/denser cap layer self-aligns positioning of unlandedvia.

In some further specific example embodiments, the cap layer meets thefollowing criteria: low leakage; extended TDDB stability; good adhesionto the base layer; greater than 5:1 etch selectivity in base layer etchchemistry. As shown in FIG. 6A, carbo-nitride materials exhibit a TDDBthat is several orders of magnitude more stable than typical forultra-low-k dielectrics. In particular, FIG. 6A shows TDDB of aoxy-carbo-nitride material (OxyCDN) compared to a typical CDO material.As shown in FIG. 6B, such carbo-nitride materials also leaksignificantly less than ultra-low-k dielectrics such as CDO. Moreover,such carbo-nitride materials exhibit a very low etch rate in typical CDOetch chemistry. For instance, selectivity etch tests show that afull-sized trench (e.g., 50 nm to 100 nm) can be etched in a CDO baselayer with very little loss from a 15 nm OxyCDN cap layer, in accordancewith an example embodiment.

As shown in FIGS. 2B and 2C, conventional processing can be carried outto pattern and etch the trenches (FIG. 2B), and then fill them withmetal (FIG. 2C). Although only two trenches are shown, any number ofmetalized trenches can be provisioned. Any suitable lithographypatterning and etch processes can be used to etch the trenches (e.g.,wet and/or dry, isotropic and/or anisotropic, etc), and the shape of thetrenches will depend on the interconnect feature being formed (e.g.,single damascene, dual damascene, etc), as will be appreciated. Themetal can be any suitable metal (e.g., copper, nickel, silver, gold,platinum, cobalt, tungsten, or alloys thereof such as copper-cobalt,copper-tin, cobalt phosphorous tungsten, nickel-phosphorous-tungsten, orany other suitable fill metal). Any suitable metal deposition process(e.g., PVD, CVD, ALD, electro or electroless deposition) may be used fordepositing the interconnect fill metal into the trenches, depending onfactors such as the trench profile and aspect ratio. In someembodiments, the trench may be lined with a barrier layer (to preventelectromigration into the insulator layers) and/or a seed layer (toassist in metalization of the trench), and/or any other desired layers.After metal deposition, the processing may further include, forinstance, planarization and cleaning to prepare the structure forsubsequent processing.

In any case, the metal lines can then be recessed below the surface ofthe cap layers, as shown in FIG. 2D. This can be achieved, for example,with citric acid/peroxide mixture or any other such chemistry routinelyused to etch copper or other typical fill metals (e.g., anyacid+peroxide). In some specific embodiments, recessing the metal linesinvolves wet etching the metal lines uniformly independent of acrystallographic orientation using a chemistry containing an etchant, anoxidizer, an inhibitor, and a solvent. In such cases, adding aninhibitor and a solvent to the etchant provides uniform etching of thefill metal material independent of a crystallographic orientation, byforming, during etching, a passivation layer on the conductive material.The wet etch chemistry containing an etchant, an oxidizer, an inhibitor,and solvent provides control over the depth of the etching of the metallines, so that only a portion (e.g., 5% to 50%) of the metal line can berecessed. In one specific such embodiment, the chemistry to wet etch themetal lines comprises between about 1% to about 40% by mass of anetchant, between about 1% to about 10% by mass of an oxidizer, andbetween about 0.1% to about 1% by mass of an inhibitor, and betweenabout 1 to about 60% by mass of an organic solvent. In one embodiment,the chemistry to etch the metal lines can include: an etchant, forexample, a glycine, an ethylenediaminetetraacetic acid, an alpha-aminoacid, a polycarboxylic acid, or a combination thereof; an oxidizer, forexample, a peroxide, an ozone, a permanganate, a chromate, a perborate,a hypohalite, or a combination thereof; an inhibitor, for example, anazole, an amine, an amino acid, a phosphate, a phosphonate, or acombination thereof; and a solvent. The solvent can be, for example, anaqueous system (e.g., water), or an organic solvent (e.g., propylenecarbonate, sulfolane, glycol ethers, methylene chloride, and the like).Numerous etch chemistries will be apparent in light of this disclosure.With further reference to FIG. 2D, the depth of the recess in theexample embodiment shown is to the top of the base insulator (e.g.,about 15 nm to 50 nm), but other embodiments may have a shallower ordeeper recess, as indicated by the dashed lines in FIG. 2D showingexample alternate etch depths as well as alternate etch patterns. Aswill be appreciated, while complete metal fill and subsequent recessingare shown in FIGS. 2C and 2D, respectively, other embodiments mayinclude a partial metal fill to the desired level within the trench,thereby eliminating or otherwise reducing the recess etch.

In this example embodiments, a conformal electromigration barrier layergenerally referred to herein as an electromigration management (EMM)layer is then deposited on the cap layer and the fill metal. The EMMlayer can be deposited using any suitable deposition technique (e.g.,ALD, CVD, PVD, etc). In some example embodiments, the EMM layer isimplemented with silicon nitride, silicon carbide, silicon carbideoxide, silicon carbide nitride, titanium, tantalum nitride, titaniumnitride, tungsten nitride, molybdenum nitride, or other suitable suchmaterials (such as those materials typically used for passivation, etchstops, and electromigration barriers). Note that the etch rate of theEMM can be lower or higher than, or the same as, the etch rates of thebilayer materials, given that the EMM equally effects the overall etchrate over both the target and off-target land pads. In some examplecases, the EMM layer has a thickness in the range of, for instance, 2 nmand 200 nm (e.g., 30 nm to 50 nm). As will be appreciated in light ofthis disclosure, the thickness of the EMM layer can vary greatly, andthe claimed invention is not intended to be limited to any particularrange of thicknesses. Indeed, some embodiments don't include an EMMlayer. The next ILD bilayer included in the stacked integrated circuitstructure can then be provided, as shown in FIG. 2F, using processes andbase/cap materials as previously described with reference to FIG. 2A.

An unlanded via is then patterned and etched, as shown in FIG. 2G. Ascan be seen, the via is shifted toward the neighboring trench, such thata portion of the via etch is over the target landing pad and a portionof the via etch is over the off-target landing pad. The via can beformed in the ILD bilayer, for example, using standard lithographyincluding via patterning and subsequent etch processes followed bypolishing, cleans, etc, as typically done. The patterning and etchprocesses can be carried out, for instance, using wet and/or dry etchtechniques. The via dimensions can vary, depending on the application.In one example case, the via opening is about 5 nm to 500 nm (e.g., 20to 45 nm), and has an aspect ratio in the range of about 8:1 to 2:1(e.g., 4:1). In other embodiments, note that the via may be part of adual damascene structure that includes the via and an upper wider trenchportion, which will be discussed in turn with reference to the exampleembodiment shown in FIGS. 5A-B. As will be appreciated, the dimensionsand aspect ratio of the desired interconnect structure will vary fromone embodiment to the next, and the claimed invention is not intended tobe limited to any particular range of dimensions or structuralconfiguration (e.g., single or dual damascene, etc).

As can be further seen with reference to FIG. 2G, the via etch isuniform as long as the etch surface is above the EMM layer. When theetching of the EMM layer and followed by the underlying ILD cap begins,the differential etch rate relative to the base insulator layer causesthe profile of the via to asymmetrically taper as indicated in FIG. 2H,thereby providing an asymmetric taper in the via bottom shape andgenerally above the off-target landing pad. This is generally becausethe cap ILD layer has a lower etch rate than the base ILD layer. Saiddifferently, the overall etch rate of materials above the target landingpad is faster than the overall etch rate of materials above theoff-target landing pad. In some example cases, the ratio of base layeretch rate to cap layer etch rate for a given etch process is greaterthan 1, and in still other cases is greater than 5 (although anysuitable differential etch rate can be used, such as 1.5:1, 2:1, 3:1,4:1, etc).

The via can then be metalized (using materials and processes similar tothose discussed with reference to FIG. 2C with respect to filling thelower metal trenches, and may or may not include additional supportlayer (e.g., diffusion barrier, nucleation layer, adhesion layer, and/orother desired layers). The net result is that the via is self-enclosedand the possibility of shorting to the neighboring fill metal to theright is reduced, as illustrated in FIG. 2I. FIG. 7A illustrates asimulation comparing electrical field strengths and locations in aconventional stacked conductive interconnect structure (such as the oneshown in FIG. 1) and a stacked conductive interconnect structureconfigured in accordance with an embodiment of the present invention(such as the one shown in FIG. 2I). As can be seen, the position of thestrongest field shifts from the ILD of the conventional structure (leftof FIG. 7A) to the cap layer in the self-enclosed asymmetric via flow(right of FIG. 7A). FIG. 7B graphically illustrates the maximumelectrical field strength (Emax) is reduced by 20-30% which translatesto a significant increase (e.g., >5× improvement) in time to dielectricbreakdown (TDDB).

Numerous variations will be apparent in light of this disclosure. Forinstance, in some embodiments, the EMM layer can be selectivelydeposited only over the fill metal areas only. Such selective depositioncan be carried out, for instance, after metal deposition andplanarization using electroless deposition of an EMM that will onlynucleate onto the fill metal. For example, electrolessly depositedcobalt will only nucleate on copper fill metal and not on the ILDmaterial. In a more general sense, the EMM material may be any metalthat can be selectively grown on the fill metal so as to effectivelyprovide a conductive passivation cap over the fill metal. Exampleconductive EMM materials that can be used include, for instance, nickel,silver, gold, platinum, cobalt, tungsten, or alloys thereof such ascopper-cobalt, copper-tin, cobalt phosphorous tungsten,nickel-phosphorous-tungsten, or any other suitable metal or alloy thatcan be selectively deposited to protect or otherwise cover the fillmetal. In such cases have a conductive EMM layer, note that the via etchprocess need not etch through the EMM layer. Rather, the EMM caneffectively be used as an etch stop and the fill metal can then bedeposited onto the EMM layer provided over the underlying fill metal. Inany such cases, an asymmetric via results from the differential etchrate with respect to the base insulator and cap layer.

Variable Thickness Electromigration Barrier Layer

FIGS. 3A-G illustrate cross-section side views of a series of integratedcircuit structures showing formation of a self-enclosed interconnectfeature configured in accordance with another embodiment of the presentinvention. In this example embodiment, the insulator layer can be asingle or continuous layer of material, rather than a multilayerstructure. Just as previously explained, this insulator layer may beformed as part of, or otherwise on, a substrate and may be configured ina number of ways and using any number of material, as will beappreciated in light of this disclosure. Factors such as desireddielectric constant can be used to select the insulator material, whichcan be, for instance, any of the previously described insulatormaterials. The insulator can be etched, metalized, and recessed as shownin FIGS. 3A, 3B, and 3C, respectively, and previous relevant discussionwith respect to FIGS. 2B, 2C, and 2D is equally applicable here. Asshown in FIG. 3D, a variable thickness EMM layer is then provisionedover the insulator and fill metal, wherein the thickness at position T₂of the EMM layer over the insulator material is at least twice as thickas the EMM layer thickness at position T₁ over the fill metal. In somecases, T₂ thickness is 3× or more greater than T₁ thickness. In a moregeneral sense, the thicknesses of the EMM layer can be set depending onthe etch rate of the EMM relative to the insulator material. In someexample cases, the variable thickness EMM can be provided using, forexample, directional deposition where thickness is selectivelycontrolled during the deposition process. In other example cases, thevariable thickness EMM layer is provided using a blanket deposition of auniform thick layer of EMM followed by selective etching (e.g.,anisotropic) to thin portions of the that EMM layer where desired. Aswill be appreciated, the actual layer thickness may vary greatly fromone point to the next along the EMM layer, and achieving a perfectlyplaner EMM layer having only two thicknesses as shown in FIG. 3D is notnecessary.

The next insulator layer can then be provided over the EMM layer, and anunlanded via can then be patterned and etched, as shown in FIG. 3E. Theprevious relevant discussion with respect to providing the nextinsulator layer and unlanded via is equally applicable here. As can befurther seen with reference to FIG. 3E, the via etch is uniform as longas the etch surface is above the EMM layer. When the etching of therelatively thicker part (of the EMM layer begins, the differential etchrate relative to the insulator layer and thin part of the EMM layercauses the profile of the via to asymmetrically taper as indicated inFIG. 3F, thereby providing an asymmetric taper in the via bottom shapeand generally above the off-target landing pad. This is generallybecause the relatively thick part (e.g., T₂ and its neighboringpositions) of the EMM layer has a lower etch rate than the overall etchrate of the insulator layer and the relatively thin part (e.g., T₁ andits neighboring positions) of the EMM layer. Said differently, theoverall etch rate of materials above the target landing pad is fasterthan the overall etch rate of materials above the off-target landingpad. In some example cases, the differential etch rate can be used, suchas 1.5:1, 2:1, 3:1, 4:1, etc), and will depend on factors such as thedifference between T₁ and T₂ and the difference in etch rates betweenthe EMM and the insulator material. The unlanded via can then bemetalized as shown in FIG. 3G and using techniques and materials aspreviously discussed, to provide is self-enclosed via having greatershorting margin and reduced electrical field in a fashion similar tothat explained with reference to FIG. 2I.

Pre-Etched/Self-Aligned Slow Etch Layer

FIGS. 4A-G illustrate cross-section side views of a series of integratedcircuit structures showing formation of a self-enclosed interconnectfeature configured in accordance with another embodiment of the presentinvention. In this example embodiment, the insulator layer can also be asingle or continuous layer of material, rather than a multilayerstructure, and the previous relevant discussion is equally applicablehere. However, prior to trench patterning and etching, a conformal anduniform layer of EMM is deposited (e.g., CVD, ALD, PVD, etc), as shownin FIG. 4A. The resulting structure can then be etched,metalized/recessed as shown in FIGS. 4B and 4C, respectively, andprevious relevant discussion with respect to FIGS. 2B, 2C, and 2D isequally applicable here. Thus, the electromigration barrier layer iseffectively pre-etched from, and self-aligned to, the target landingpads.

The next insulator and EMM layers can then be provided over thepatterned EMM layer and fill metal as shown in FIG. 4D, and an unlandedvia can then be patterned and etched, as shown in FIG. 4E. The previousrelevant discussion with respect to providing the next insulator and EMMlayers and unlanded via is equally applicable here. As can be furtherseen with reference to FIG. 4E, the via etch is uniform as long as theetch surface is above the EMM layer. When the etching of the EMM layerbegins, the differential etch rate relative to the insulator layercauses the profile of the via to asymmetrically taper as indicated inFIG. 4F, thereby providing an asymmetric taper in the via bottom shapeand generally above the off-target landing pad. This is generallybecause the EMM layer has a lower etch rate than the etch rate of theinsulator layer. Said differently, the overall etch rate of materialsabove the target landing pad is faster than the overall etch rate ofmaterials above the off-target landing pad. In some example cases, thedifferential etch rate can be used, such as 1.5:1, 2:1, 3:1, 4:1, etc),and will depend on the thickness of the EMM layer and the difference inetch rates between the EMM and the insulator material. The unlanded viacan then be metalized as shown in FIG. 4G and using any suitabletechniques and materials such as those previously discussed, to provideis self-enclosed via having greater shorting margin and reducedelectrical field in a fashion similar to that explained with referenceto FIG. 2I.

FIG. 4G′ illustrates a cross-section side view of an integrated circuitstructure having a self-enclosed interconnect feature in accordance withanother embodiment of the present invention. As can be seen, thisexample embodiment is similar to the one shown in FIG. 4G (and theprevious relevant discussion equally applies here), except that thisembodiment is implemented with fast and slow etch layers. Thus, whilethe slow etch layer can be an electromigration barrier layer, it neednot be. Rather, it can be any suitable material having an etch rate thatis slower than the fast etch layer. Likewise, the fast etch layer neednot be any particular material; rather, it can be any suitable materialhaving an etch rate that is faster than the slow etch rate layer. Inaddition to their respective etch rates, the slow and fast etch layermaterials can be selected, for instance, based on their desiredsemiconductor characteristics (e.g., dielectric constant, ability toinhibit diffusion and/or electromigration, etchability with respect to agiven etch chemistry or process, etc), cost, accessibility, and/or othersuch pertinent factors. In any case, the slow etch rate layer iseffectively pre-etched from, and self-aligned to, the target landingpads. The next fast etch and slow etch layers can then be provided overthe patterned slow etch layer and fill metal as previously discussedwith respect to FIG. 4D, and an interconnect feature can then bepatterned and etched, such as the unlanded via previously discussed withrespect to FIG. 4E. The interconnect feature can then be metalized aspreviously discussed, to provide is self-enclosed interconnect feature.

Other variations will be apparent in light of this disclosure. Forinstance, in one such variation, the slow etch layer can be grown with aselective deposition technique after deposition and planarization of thefill metal. In such cases, recessing of the metal could be avoided.

FIG. 5A shows a specific example embodiment where the underlying metallanding pad is a metal line of a lower layer in a dynamic random accessmemory (DRAM) integrated circuit structure. Note, however, any number ofother multi-layer integrated circuits may have a similar stackedstructure. As can be seen, the integrated circuit that includes aplurality of stacked interconnect layers on top of the substrate. Inthis example case, the substrate is configured with various DRAM cellcomponents integrated therein, such as access transistor T and word lineWL. Such DRAM devices typically include a plurality of bit cells, witheach cell generally including a storage capacitor communicativelycoupled to a bitline by way of an access transistor that is gated by aword line. Other typical DRAM components and features not shown can alsobe included (e.g., row and column select circuitry, sense circuitry,power select circuitry, etc). Each layer includes various metal lines(M1, M1′, M2, M2′ . . . M9, and M9′) and corresponding vias (V0, V0′,V1, V1′ . . . V8 and V8′) formed within an interlayer dielectric (ILD)material. Note that the layout shown is not intended to implicate anyparticular feature spacing or density. Rather, this layout is simply anarbitrary example, and any number of layout designs can benefit from anembodiment of the present invention, where conductive interconnectfeatures are formed as described herein. Each layer in this examplestructure is generally isolated or otherwise demarcated from neighboringlayers by a slow etch layer. In contrast, the ILD material provides afast etch layer, as generally indicated in FIG. 5A. In addition, eachmetal line and via of this example embodiment is configured with anoptional barrier layer (e.g., tantalum or other diffusion barrier).Other embodiments may include fewer or more such layers (e.g.,nucleation layers, adhesion layers, etc).

In this particular example case, FIG. 5A shows how via V1 is unlandedand electrically connects metal line M2 to the underlying metal line M1.Note how this unlanded via can be one of many vias, and can also be theonly one that is unlanded, or one of many unlanded vias. The off-targetlanding may be, for instance, due to registration errors, or may beintentional. In any case, and as will be appreciated in light of thisdisclosure, the fast and slow etch layers effectively cause adifferential etch rate that yields an interconnect feature having anasymmetric taper. Thus, for instance, the ratio of fast etch layer etchrate to slow etch layer etch rate for a given etch process is greaterthan 1, and in still other specific cases is greater than 5 (althoughany suitable differential etch rate can be used, such as 1.5:1, 2:1,3:1, 4:1, etc).

Any number of materials can be used to implement the slow and fast etchrate layers, as previously explained. In some specific exampleembodiments, the fast etch layer material can be, for example, anultra-low dielectric material such as a porous SiCOH having a dielectricconstant k of less than 2.3 and porosity greater than 35 volume %. Insuch example cases, the slow etch layer material can be, for instance, arelatively denser SiCOH having a dielectric constant k in the range ofabout 2.8 to 3.0, and a porosity of less than 10 volume % or aplasma-enhanced CVD (PECVD) oxide (e.g., silicon dioxide) or nitride(e.g., silicon nitride).

In an embodiment, a device may include one or more lower levels ofmetallization that have unlanded vias with asymmetric tapers asdescribed herein, while also having one or more higher levels ofmetallization where the unlanded vias lack such asymmetric tapers. Forexample, the lower layers that include M1/V0 and M2/V1 may includeasymmetrically tapered unlanded vias as described herein. In that samedevice, the upper layers that include M8/V7 and M9/V8 may have unlandedvias that do not asymmetrically taper, but instead the unlanded portionof the via may extend down to the metal line below without taperingsubstantially more or differently than the side of the via that extendsdown to the lower metal surface. Such higher metal layers may simplyhave an interlayer dielectric (ILD) material adjacent the lower line andvia, with an etch stop layer above the ILD and another layer of ILDabove the etch stop layer. Via holes are created by etching through theupper ILD and etch stop, and unlanded portions of the holes extendfarther down into the lower ILD material than if the slow etch/fasteretch material scheme and/or recessed metal techniques described hereinwere used, and do not significantly asymmetrically taper.

FIG. 5B illustrates an expanded view of the unlanded via shown in FIG.5A, and configured in accordance with one embodiment of the presentinvention. As can be seen, FIG. 5B is drawn to reflect real worldprocess limitations, in that the features are not drawn with preciseright angles and straight lines. Via V1 shows the asymmetric taper, aswell as the normal profile of via V1 (designated with dashed line), ifnot for the presence of the slow etch layer. In this example case, theasymmetric taper effectively reduces the normal profile of the via V1 byabout 25%. The normal profile for the unlanded portion of the via can bereadily predicted or otherwise determined by looking at the profile ofthe landed portion, which has not been interfered with by the slow etchlayer. Other embodiments may include a larger profile reduction (e.g.,80% to 95%) or a smaller reduction (5% to 15%). The amount of thereduction will depend on factors such as desired packing density anddesired conductivity for the interconnect. This profile reduction can bemeasured, for instance, at its widest point, which in this example isgenerally at the interface between metal M1 and the unlanded via V1.

The presence of a profile reduction can be determined, for instance, bytaking a cross-section of the via at any point or plane and identifyingthat the unlanded profile bumps in toward the center axis of the via.The shape of the bump can vary from case to case, but in some cases,looks like a concave depression in the via sidewall that contains slowetch material. Further note that the top of the depression where thetaper begins (at the interface that transition from fast to slow etchlayers) can be shallower than the bottom of the depression near theon-target landing pad. As shown in this example, the taper effectivelyplateaus or otherwise self-aligns with the interface between the metalM1 and the fast etch layer. In still other embodiment, note that the topof the depression can have the same depth as the bottom of thedepression (almost square or rectangular in nature). Such an asymmetrictaper shape may result, for instance, when the ratio of fast etch layeretch rate to slow etch layer etch rate is greater than, for example, 5.Such a differential etch ratio indicates that the edge of the slow edgematerial will not be substantially diminished or otherwise furtherrounded during the landing etch process. Numerous shapes and profilesfor the asymmetric taper will be apparent in light of this disclosure,and the claimed invention is not intended to be limited to anyparticular taper type. In various example embodiments, the taper may beangular (e.g., where top of taper is narrower than bottom of taper) orstraight (e.g., where top and bottom of taper are about the same), orhave any geometric profile, so long as the profile of the unlanded viasidewall is moved toward the center of the via more so than the profileof the landed via sidewall.

In some cases, both sides of the via will naturally taper as a result ofthe etching process. However, absent the techniques described herein,this taper is substantially symmetrical, with all sides tapering roughlythe same amount. Some embodiments of an asymmetrical taper, on the otherhand, will taper more adjacent the unlanded portion of the via thanadjacent landed portions. In some embodiments the difference betweensymmetrically tapering and asymmetrically tapering may be described asthe symmetrically tapering via having angles of opposing sides at agiven distance from the lower metal to which contact is to be made thatare within 10% of each other, while an asymmetrically tapering via mayhave angles of opposing sides at a given distance from the lower metalto which contact is to be made that are greater than about 15%different. Similarly, the concavity described above can be identified insome embodiments by having a landed side of a via with a sidewall thattapers in a substantially continuous manner as it approaches the uppersurface of the metal to which it will make contact. The unlanded,asymmetrically tapered, side has a sidewall that substantially followsthe taper of the landed side in an upper portion, then has a portionthat is significantly more horizontal than the corresponding portion ofthe other opposing sidewall, then starts to return to an angle more andmore similar to the angle of the opposing sidewall as it gets closer tothe top of the metal to which it makes contact. Significantly morehorizontal may mean an angle difference of ten degrees, twenty degrees,thirty degrees or other angle differences in various embodiments usingdifferent materials, etchants, metal recess depths and/or othervariations. In an embodiment, a middle third of a via may have sidewallswith an average angle, and as the via approaches the upper surface ofthe metal to which it makes contact, the landed sidewall of the via thatis closer to the middle of the metal continues to have an angle roughlythe same as the average angle while the unlanded sidewall of the viathat is farther from the middle of the metal has a sidewall angle thatgets significantly farther from the average angle. In a few embodimentsthe “roughly the same” and “significantly farther” angles may be (a)within five degrees and more than seven degrees, (b) within threedegrees and more than five degrees, (c) within five degrees and morethan ten degrees, respectively. Other examples may be readily seen inother embodiments. These are non-limiting examples and one can readilyperceive, in light of this disclosure, when a via is asymmetrical, andparticularly perceive when a via has been made asymmetrical by inclusionof a recessed lower metal and/or slower-etching region as describedherein.

FIG. 5C illustrates an expanded view similar to that shown in 5B, asmight be found in one embodiment of the present invention. In theembodiment of FIG. 5C, the M1 material is not recessed to the bottom ofthe slow etch layer, but instead a portion of M1 remains above thebottom of the slow etch layer. When the via hole is formed, it may beformed using a method such as etching or another suitable method, and tobe sure the dielectric material is removed from the surface of M1, itmay be slightly overetched so a portion of the slow etch layer adjacentto a side wall of M1 is also removed. The via hole thus extends slightlypast the top surface of M1, and in some cases may extend into the fastetch layer. The conductive material formed in the via also extendsslightly lower than the upper surface of M1. Despite this fact, the viastill has an asymmetric taper on the unlanded side as variouslydescribed herein.

Example System

FIG. 8 illustrates a computing system 1000 implemented with one or moreintegrated circuit structures configured and/or otherwise fabricated inaccordance with an example embodiment of the present invention. As canbe seen, the computing system 1000 houses a motherboard 1002. Themotherboard 1002 may include a number of components, including but notlimited to a processor 1004 and at least one communication chip 1006,each of which can be physically and electrically coupled to themotherboard 1002, or otherwise integrated therein. As will beappreciated, the motherboard 1002 may be, for example, any printedcircuit board, whether a main board or a daughterboard mounted on a mainboard or the only board of system 1000, etc. Depending on itsapplications, computing system 1000 may include one or more othercomponents that may or may not be physically and electrically coupled tothe motherboard 1002. These other components may include, but are notlimited to, volatile memory (e.g., DRAM), non-volatile memory (e.g.,ROM), a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, atouchscreen controller, a battery, an audio codec, a video codec, apower amplifier, a global positioning system (GPS) device, a compass, anaccelerometer, a gyroscope, a speaker, a camera, and a mass storagedevice (such as hard disk drive, compact disk (CD), digital versatiledisk (DVD), and so forth). Any of the components included in computingsystem 1000 may include one or more integrated circuit structuresconfigured with one or more self-enclosed conductive interconnectfeatures having an asymmetric profile. These integrated circuitstructures can be used, for instance, to implement an on-board processorcache or memory array or other circuit feature that includesinterconnects. In some embodiments, multiple functions can be integratedinto one or more chips (e.g., for instance, note that the communicationchip 1006 can be part of or otherwise integrated into the processor1004).

The communication chip 1006 enables wireless communications for thetransfer of data to and from the computing system 1000. The term“wireless” and its derivatives may be used to describe circuits,devices, systems, methods, techniques, communications channels, etc.,that may communicate data through the use of modulated electromagneticradiation through a non-solid medium. The term does not imply that theassociated devices do not contain any wires, although in someembodiments they might not. The communication chip 1006 may implementany of a number of wireless standards or protocols, including but notlimited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE,GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The computing system 1000 may include a plurality ofcommunication chips 1006. For instance, a first communication chip 1006may be dedicated to shorter range wireless communications such as Wi-Fiand Bluetooth and a second communication chip 1006 may be dedicated tolonger range wireless communications such as GPS, EDGE, GPRS, CDMA,WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integratedcircuit die packaged within the processor 1004. In some embodiments ofthe present invention, the integrated circuit die of the processorincludes onboard memory circuitry that is implemented with one or moreintegrated circuit structures configured with one or more self-enclosedconductive interconnect features having an asymmetric profile asvariously described herein. The term “processor” may refer to any deviceor portion of a device that processes, for instance, electronic datafrom registers and/or memory to transform that electronic data intoother electronic data that may be stored in registers and/or memory.

The communication chip 1006 may also include an integrated circuit diepackaged within the communication chip 1006. In accordance with somesuch example embodiments, the integrated circuit die of thecommunication chip includes one or more devices implemented with one ormore integrated circuit structures formed as variously described herein(e.g., on-chip processor or memory having an asymmetric interconnectfeature). As will be appreciated in light of this disclosure, note thatmulti-standard wireless capability may be integrated directly into theprocessor 1004 (e.g., where functionality of any chips 1006 isintegrated into processor 1004, rather than having separatecommunication chips). Further note that processor 1004 may be a chip sethaving such wireless capability. In short, any number of processor 1004and/or communication chips 1006 can be used. Likewise, any one chip orchip set can have multiple functions integrated therein.

In various implementations, the computing system 1000 may be a laptop, anetbook, a notebook, a smartphone, a tablet, a personal digitalassistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer,a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, the system 1000may be any other electronic device that processes data or employsintegrated circuit features configured with one or more self-enclosedconductive interconnect features having an asymmetric profile asvariously described herein.

Numerous embodiments will be apparent, and features described herein canbe combined in any number of configurations. One example embodiment ofthe present invention provides a semiconductor device. The devicecomprises a first insulator structure having a metal feature therein,and a second insulator structure having a metal feature therein. Thedevice further includes an intervening layer between the first andsecond insulator structures, wherein the first insulator structure,intervening layer, and second insulator structure are arranged in astack. The intervening layer can be, for instance, an electromigrationbarrier layer, a passivation layer, an etch stop layer, or any otherdesired material layer or multiple such layers or hybrid layer (e.g.,etch stop and electromigration barrier layer). The device furtherincludes a conductive interconnect feature connecting the metal featureof the first insulator structure to the metal feature of the secondinsulator structure, the conductive feature passing through theintervening layer and asymmetrically tapers to land on the metal featureof the first insulator structure. In some cases, the conductiveinterconnect feature is an unlanded via. In some cases, the asymmetrictaper of the conductive interconnect feature increases the distancebetween the metal feature of the first insulator structure and aneighboring metal feature in the first insulator structure, relative tothe distance between those two metal features if no asymmetric taper waspresent. In some cases, the metal feature of the first insulatorstructure upon which the conductive interconnect feature lands comprisesa target landing pad, and for a given etch process, the overall etchrate of materials above the target landing pad is faster than theoverall etch rate of materials above an off-target landing pad below theasymmetric taper. In some cases, each of the first and second insulatorstructures comprises a multilayer structure of two or more insulatorlayers, and the asymmetric taper is formed in at least one of the two ormore insulator layers. In some specific cases, each of the first andsecond insulator layers comprises a bilayer structure, each bilayerstructure including a base layer and a cap layer. In some such specificcases, the ratio of base layer etch rate to cap layer etch rate for agiven etch process is greater than 5. In some cases, the asymmetrictaper is at least partially formed in the cap layer of the firstinsulator layer. In some cases, the base layer comprises an ultra-lowdielectric material having a dielectric constant below that of silicondioxide and the cap layer comprises a dielectric material having highera density greater than that of the base layer. In some cases, theintervening layer has a variable thickness in that it is thinner at aposition over the metal feature of the first insulator structurerelative to barrier layer thickness at a position over other portions ofthe first insulator structure. In one such case, the intervening layerthickness at a position over the metal feature of the first insulatorstructure is more than two times thinner than intervening layerthickness at a position over the other portions of the first insulatorstructure. In some cases, for a given etch process, the overall etchrate of insulator material and thinner intervening layer material isfaster than the overall etch rate of insulator material and thickerintervening layer material is greater than 1. In one specific such case,the ratio is greater than 5. In some cases, the asymmetric taper is atleast partially formed in the intervening layer (e.g., in the thickerpart). In some cases, the intervening layer has a uniform thickness andis not on the metal feature of the first insulator structure (because itwas etched away when the trench for the metal feature was etched). Insome such cases, the metal feature of the first insulator structure uponwhich the conductive interconnect feature lands comprises a targetlanding pad, and for a given etch process, the ratio of overall etchrate of materials above the target landing pad to overall etch rate ofmaterials above an off-target landing pad below the asymmetric taper isgreater than 5. In some such cases, the asymmetric taper is at leastpartially formed in the intervening layer. In some such cases, each ofthe first and second insulator structures is a continuous layer of thesame insulator material. Numerous variations will be apparent in lightof this disclosure. For example, another embodiment provides anelectronic system comprising the device as variously described in thisparagraph. The electronic system may be, for example, a computing system(e.g., laptop, desktop, portable communication device, etc).

Another embodiment of the present invention provides a multilayerintegrated circuit device. In this example case, the device includes afirst insulator structure having one or more metal features therein, anda second insulator structure having one or more metal features therein.The device further includes an electromigration barrier layer betweenthe first and second insulator structures, wherein the first insulatorstructure, electro migration barrier, and second insulator structure arearranged in a stack. The device further includes a conductiveinterconnect feature connecting one of the metal features of the firstinsulator structure to one of the metal features of the second insulatorstructure, the conductive feature passing through the electromigrationbarrier layer and asymmetrically tapers to land on the correspondingmetal feature of the first insulator structure. The asymmetric taper ofthe conductive interconnect feature increases the distance between thecorresponding metal feature of the first insulator structure and aneighboring metal feature in the first insulator structure, relative tothe distance between those two metal features if no asymmetric taper waspresent. In some cases, each of the first and second insulatorstructures comprises a multilayer structure of two or more insulatorlayers, and the asymmetric taper is formed in at least one of the two ormore insulator layers. In some cases, the asymmetric taper is at leastpartially formed in the electromigration barrier layer. In some suchcases, each of the first and second insulator structures is a continuouslayer of the same insulator material.

Another embodiment of the present invention provides a method forforming a semiconductor device. The method includes providing a firstinsulator structure having a metal feature therein, and providing asecond insulator structure having a metal feature therein. The methodfurther includes providing an electromigration barrier layer between thefirst and second insulator structures, wherein the first insulatorstructure, electromigration barrier, and second insulator structure arearranged in a stack. The method further includes providing a conductiveinterconnect feature connecting the metal feature of the first insulatorstructure to the metal feature of the second insulator structure, theconductive feature passing through the electromigration barrier layerand asymmetrically tapers to land on the metal feature of the firstinsulator structure. In some such cases, the conductive interconnectfeature is an unlanded via. In some cases, the metal feature of thefirst insulator structure upon which the conductive interconnect featurelands comprises a target landing pad, and for a given etch process, theoverall etch rate of materials above the target landing pad is fasterthan the overall etch rate of materials above an off-target landing padbelow the asymmetric taper.

The foregoing description of example embodiments of the invention hasbeen presented for the purposes of illustration and description. It isnot intended to be exhaustive or to limit the invention to the preciseforms disclosed. Many modifications and variations are possible in lightof this disclosure. It is intended that the scope of the invention belimited not by this detailed description, but rather by the claimsappended hereto.

1. An integrated circuit comprising: a first insulator structure havinga first metal feature therein; a second insulator structure having asecond metal feature therein; an intervening layer between the first andsecond insulator structures, the intervening layer including aprotrusion; and a conductive interconnect feature connecting the firstmetal feature to the second metal feature, the conductive interconnectfeature passing through both the intervening layer and the secondinsulator structure in at least one horizontal common plane, wherein theconductive interconnect feature includes an asymmetric taper that causesa depression on only one side of the conductive interconnect feature,wherein the depression at least partially tapers towards an opposingside of the conductive interconnect feature to cause the conductiveinterconnect feature to at least partially land on the first metalfeature, and wherein the depression of the conductive interconnectfeature is conformal to the protrusion of the intervening layer.
 2. Theintegrated circuit of claim 1, wherein the conductive interconnectfeature only partially lands on the first metal feature.
 3. Theintegrated circuit of claim 2, wherein material of the second insulatorstructure is on a remainder of the first metal feature.
 4. Theintegrated circuit of claim 2, wherein material of the intervening layeris on a remainder of the first metal feature.
 5. The integrated circuitof claim 1, wherein the intervening layer is not present over the firstmetal feature.
 6. The integrated circuit of claim 1, wherein theintervening layer has a variable thickness such that the interveninglayer is thinner at a location above the first metal feature relative toa location on the first insulator structure.
 7. The integrated circuitof claim 1, wherein the protrusion of the intervening has a thicknessless than a maximum thickness of the intervening layer.
 8. Theintegrated circuit of claim 1, wherein the intervening layer includes atleast one of nitrogen or carbon.
 9. The integrated circuit of claim 1,further comprising an additional layer between the intervening layer andthe second insulator structure, the additional layer including at leastone of nitrogen or carbon.
 10. The integrated circuit of claim 1,wherein no discernible interface exists between the second metal featureand the conductive interconnect feature.
 11. The integrated circuit ofclaim 1, wherein the protrusion is integral with another portion of theintervening layer that is on the first insulator structure.
 12. Theintegrated circuit of claim 1, wherein the second insulator structureand the intervening layer include the same material composition but thematerial of the second insulator structure is relatively more porousthan the material of the intervening layer.
 13. The integrated circuitof claim 1, wherein the first and second insulator structures includeone or more ultra-low-k dielectric materials.
 14. A computing systemcomprising the integrated circuit of claim
 1. 15. An integrated circuitcomprising: a first insulator structure having a first metal featuretherein, the first insulator structure including one or more ultra-low-kdielectric materials; a second insulator structure having a second metalfeature therein, the second insulator structure including one or moreultra-low-k dielectric materials; a first intervening layer between thefirst and second insulator structures, the first intervening layerincluding a protrusion; a second intervening layer between the firstintervening layer and the second insulator structure, the secondintervening layer including at least one of nitrogen or carbon; and athird metal feature connecting the first metal feature to the secondmetal feature, no discernible interface existing between the secondmetal feature and the third metal feature, the third metal featureincluding an asymmetric taper that causes a depression on only one sideof the third metal feature, wherein the depression at least partiallytapers towards an opposing side of the third metal feature to cause thethird metal feature to at least partially land on the first metalfeature, and wherein the depression of the third metal feature isconformal to the protrusion of the first intervening layer.
 16. Theintegrated circuit of claim 15, wherein the third metal feature passesthrough all of the first intervening layer, the second interveninglayer, and the second insulator structure in at least one horizontalcommon plane.
 17. The integrated circuit of claim 15, wherein the thirdmetal feature only partially lands on the first metal feature.
 18. Theintegrated circuit of claim 15, wherein material of the secondintervening layer is on a portion of the first metal feature.
 19. Theintegrated circuit of claim 15, wherein the protrusion in the firstintervening layer causes a relative increase in distance between thethird metal feature and an additional metal feature in the firstinsulator structure than if the protrusion were not present.
 20. Acomputing system comprising the integrated circuit of claim 15.